1. Field of the Invention
This invention relates to a data prefetch buffer for a computer system, and to an information processing system to which the data prefetch buffer is applied.
2. Description of the Related Art
In computer systems, and workstations in particular, the performance has recently being improved remarkably by the development of high-performance RISC processors. Generally a RISC processor includes a small-capacity cache memory which enables high-speed access, and a low-speed large-capacity main memory. When the amount of data to be processed is small and when no cache errors occur, it is possible to bring out the performance of a RISC processor to it's full extent. However, when the amount of data to be processed is large so that when many cache errors occur, the RISC processor does not execute its program until it has read data from a main memory, so this waiting time reduces the performance. Assuming that the access time of its main memory is the same, every high-speed processor must wait for the same time. Therefore, in the case where many cache errors occur, despite all attempts to improve the performance of the processor, it is impossible to improve the overall processing performance.
It is common knowledge that a prefetch buffer may be used to solve the foregoing problem. This prior art is exemplified by a paper entitled "Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers" (The 17th Annual International Symposium on Computer Architecture Conference Proceedings, May 1990, pages 364-373) of Norman P. Jouppi. According to this prior concept, when a cache error occurs, data to be fetched from the main memory is read in advance in a small-capacity buffer to eliminate any overhead due to accessing to the main memory.
Other prior art publications concerning the concept of using a prefetch buffer are, for example, Japanese Patent Laid-Open Publications (KOKAI) Nos. SHO 53-134334, SHO 63-75934 and HEI 2-87229, and U.S. Pat. No. 4,714,994.
With this prior prefetch buffer, since instructions of a program are generally executed in the order of address, data to be prefetched are usually limited to data having an address immediately subsequent to data requested from the processor. Prefetching for special cases such as branching and looping processes has also been proposed.
However, if the request address value varies continuously in the backward direction, or if the request addresses are discontinuous, the hit ratio of the prefetch buffer will be deteriorated, and so the performance will be lowered.